1. Field of the Invention
This invention relates to an analog-to-digital converter offset correction means, and more particularly, to a means for the correction of DC offsets inherent in the operation of analog-to-digital converters. The correction for DC offsets in analog-to-digital converters is accomplished with a circuit which utilizes a digital integration process in a negative feedback correction loop.
2. Discussion of the Prior Art
Analog-to-digital converters convert analog signals into digital signals, which are approximations of the original analog signal, by quantizing the analog signal into a predetermined number of discrete levels. There are a variety of analog-to-digital conversion techniques including the successive approximation technique, the integrating technique and the parallel (flash) technique, and in each of these techniques there is an inherent DC offset. The DC offset is a voltage that appears or exists at the output of the analog-to-digital converter at all times. The DC offset arises from the various forms of noise in the surrounding environment of the analog-to-digital converter which effect the internal circuitry of the analog-to-digital converter. The DC offset displaces or biases the digitized output signal by a specific amount and which when coupled with the quantizing approximations, results in an output signal that is not a true representation of the original analog signal waveform In addition, errors in the quantizing approximations are inherent in the conversion process and can only be reduced, not eliminated, by increasing the resolution of the analog-to-digital converter. However, the DC offset, while inherent in any type of electrical circuitry, can be essentially eliminated in order to provide accurate digitized signal waveforms.
There are two fundamental approaches to the correction of DC offset in analog-to-digital converters; namely, a software approach and a hardware approach. The software approach requires a processor to compute the DC offset, which utilizes valuable processing time. The hardware approach avoids the need to tie up valuable processing time and requires approximately 1000 times less time than the software correction approach requires. In the patent art, there are numerous examples of hardware implementations for the correction for DC offsets in analog-to-digital converters.
U.S. Pat. No. 4,228,423 to Schwerdt discloses an offset correction apparatus for a successive approximation analog-to-digital converter. This disclosure specifically deals with the DC offset correction in analog-to-digital converters which contain internal digital-to-analog converters. In addition, the invention requires internal modifications to the analog-to-digital converter as well as two external timing signals to control the operation of the offset correction circuit.
U.S. Pat. No. 4,308,524 to Harrison et al. discloses a fast high resolution predictive analog-to-digital converter with error correction. This invention provides for the improved resolution of a fast analog-to-digital converter and the reduction of error of sample and hold amplifiers. Data correction values are updated and applied on a sample to sample basis, and occurs simultaneously with the actual data conversion. The corrections are calculated by subtracting the previous sample value from the current sample. This method for correction will cause erroneous results when the analog signal is rapidly varying in amplitude.
U.S. Pat. No. 4,097,860 to Araseki et al. discloses an offset compensating circuit. The method employed requires that a preset offset level be reached before compensation is applied and in order to set the preset level, a prior knowledge of the input signal levels as well as the converter characteristics is needed. The compensation is not exact because it is either zero or the preset level.
U.S Pat. No. 4,590,458 to Evans et al. discloses a system for reducing offset in an analog to digital conversion system. The DC offset correction is achieved by adding or subtacting from a counter. The decision to add or subtract is made by sampling the grounded input between conversions The sign bit of this sample determines the addition or subtraction of one count. Some time is required after initial turn on for the DC offset correction value to reach a steady state level. There will be a similar time delay whenever the DC offset changes rapidly with time.